1. Field of the Invention
The invention relates to a backside-illuminated solid-state imaging device, a method of fabricating the backside-illuminated solid-state imaging device, and a camera.
2. Description of the Related Art
In a CMOS type solid-state imaging device, there has been disclosed a backside-illuminated solid-state imaging device for improving photoelectric conversion efficiency and sensitivity to incident light. In the backside-illuminated solid-state imaging device, light is illuminated from backside of the solid-state imaging device. The backside-illuminated solid-state imaging device is configured to include a semiconductor substrate on which photodiodes as photoelectric converters, pixel transistors, a plurality of wiring layers forming a signal circuitry, and the like are formed (see Japanese Unexamined Patent Application Publication No. 2005-347707, and Japanese Unexamined Patent Application Publication No. 2005-353631).
The backside-illuminated solid-state imaging device includes a pad portion formed on a rear side of the semiconductor substrate that can supply predetermined electrical potential to a multilayer interconnect formed on a front-surface side of the semiconductor substrate.
FIG. 1 is a schematic cross-sectional configuration diagram illustrating a backside-illuminated solid-state imaging device according to the related art. The cross-sectional configuration diagram in FIG. 1 specifically illustrates a region that includes a pad portion 60 formed in a peripheral region of a rear side of the backside-illuminated solid-state imaging device.
The backside-illuminated solid-state imaging device 70 includes an imaging region in which photodiodes 54 each used as a photoelectric converter and a plurality of pixels including pixel transistors (MOS transistors), a peripheral circuitry are formed on a semiconductor Si layer 53, and a pad portion 60 formed in a peripheral region of a rear side thereof. Although not shown in the figure, the pixel transistors each forming a pixel are formed on a front-surface side of the Si layer 53. Further, multi-layer interconnects 52 (e.g., Cu interconnects) and a plurality of wiring layers 51 including a wire-bonding AL interconnect 52a are formed on a surface of the Si layer 53 via an interlayer dielectric 61. A supporting substrate 50 formed of a silicon substrate is formed on a front-surface side of the plurality of wiring layers 51.
In contrast, an insulating film 55 used as an antireflective film, a shield film 56, and a passivation film 57 are multiply layered in this order on a rear side of the Si layer 53. Further, on-chip color filters are formed on the passivation film 57 corresponding to the imaging region, and on-chip microlenses 53 are formed on the passivation film 57. The imaging region includes an optical black region formed outside of an effective pixel region for specifying black levels of images. Pixels and color filters similar to the pixels in the effective pixel region are formed in the optical black region. The shield film 56 is formed over an entire surface including other pixel transistors and peripheral circuitries except for light-receiving portions in the effective pixel region, namely, the photodiodes 54 and pad portions 60.
The pad portion 60 includes an opening 62 to expose the AL interconnect 52a connected to predetermined interconnects 52 of the plurality of wiring layers 51. Specifically, after the on-microchiplenses have been formed, an opening 62 is formed such that desired Al interconnects 52a are exposed from a rear surface of the backside-illuminated solid-state imaging device 70 towards a front-surface thereof on which the multilayer interconnection layer 51 is formed, thereby forming the pad portion 60 for taking out an electrode. In this process, the pad portion 60 is formed by etching the Si layer 53 including photodiodes 54 formed thereon, an insulating film 55 formed on an incident light surface of the Si layer 53, an interlayer dielectric 61 of the plurality of wiring layers 51, and the like. In the pad portion 60 formed in this manner, for example, Au fine wires (so called bonding wires) 63 are connected to Al interconnects 52a (wire-bonding) that are exposed from the opening 62.
However, in the related art backside-illuminated solid-state imaging devices, since the Si layer 53 is exposed from an internal sidewall of the pad portion 60, the Si layer 53 and the Au fine wires 63 are brought into contact when the Au fine wires 63 are wire-bonded to the Al interconnects 52a in the pad portion 60. Therefore, current is likely to flow between a well region (e.g., p-type well region) for the Au fine wires 63 having ground potential and a region having different potential. That is, leak current flows from the Au fine wires 63 to the Si layer 53.
The interlayer dielectric 61 of the plurality of wiring layers 51 is exposed from the internal sidewall of the opening 62 forming the pad portion 60. The interlayer dielectric 61 includes metal used as the interconnects 52 forming a signal circuitry. Thus, only providing the interlayer dielectric 61 that is exposed from the opening 62 may not be sufficient to prevent the interconnects 52 from absorbing moisture. That is, the interconnects 52 may deteriorate under a high-humidity environment. In the cutting-edge CMOS process, an insulating film with a small dielectric constant (a Low-κ dielectric) is used as the interlayer dielectric 61 of the plurality of wiring layers 51; however, a film property of the Low-κ dielectric may also deteriorate under such high-humidity environment, thereby exhibiting no moisture resistance in the interlayer dielectric 61.
Japanese Unexamined Patent Application Publication No. 2005-347707 discloses a pad portion configuration including an insulating film formed on the sidewall thereof. However, in this configuration, since the insulating film is only formed for the pad portion, the number of steps for fabricating backside-illuminated solid-state imaging devices may increase. Moreover, the pad portion may be coated with an organic film, however, the organic film may not be able to cover the pad portion sufficiently (not enough coverage), thereby exhibiting not enough reliability.
Further, since the related art shield film used in the backside-illuminated solid-state imaging device is electrically floating, electrical potential is not stabilized. As a result, the electrical potential of the shield film may cause an adverse effect on pixels of the solid-state imaging device.